1. Technical Field
The present invention relates to a circuit for compensating for the declination of balanced impedance elements and a frequency mixer, and more particularly to a circuit for reducing secondary-order inter modulation distortion (IMD2) in a direct conversion receiver (DCR).
2. Discussion of the Related Art
Recently, various communication circuits have been integrated into a single semiconductor chip using a system-on-a-chip (SOC) design. For example, a typical radio frequency (RF) transmitter and receiver circuit used by a mobile communications device has been integrated into a single integrated circuit (IC) using a SOC design.
Balanced impedance elements are commonly used in SOC designs. Each of the impedance values of the balanced impedance elements may typically deviate from the designed (or desired) impedance values and have a variation (or declination) from one another due to certain technical limits resulting from the manufacture of the semiconductor device. Such technical limits or constraints that occur during manufacturing are, for example, mismatch of the area of the impedance elements and mismatch of the concentration of impurities. In a typical RF receiver circuit, the impedance variation of the balanced impedance elements may distort signals and deteriorate communication qualities.
FIG. 1 is a block diagram showing a conventional DCR. Referring to FIG. 1, the DCR converts an input RF signal into a baseband signal having an in-phase (I) component and a quadrature (Q) component instead of an intermediate frequency (IF) signal. An RF signal received from an antenna 10 is input to a low noise amplifier (LNA) 12 and is applied to mixers 14 and 16.
The mixer 14 mixes the RF signal output from the LNA 12 with a first local oscillating signal, such as cos(ωt). The local oscillating signal is generated from a local oscillator (LO) 20 and has the same frequency as a carrier frequency (fc) of the RF signal. The mixer 16 mixes the RF signal output from the LNA 12 with a second local oscillating signal, for example sin(ωt), having a phase difference of more than π/2 with respect to the first oscillating signal.
The mixers 14 and 16 generate a baseband signal that has a carrier frequency of 2*fc and an I component and Q component. Subsequently, some of the harmonics in the baseband signal are removed by low pass filters 22 and 24, and the baseband signal is then amplified by amplifiers 26 and 28.
The DCR of FIG. 1 has a basic circuit structure that occupies a small surface area on an IC and thus may easily be integrated into a SOC design. Because the DCR occupies such a small area, it may be manufactured at a low price. However, the DCR has certain disadvantages. For example, the mixers 14 and 16 generate a IMD2 because the mixers 14 and 16 are non-linear devices. Thus, the mixers 14 and 16 cause a direct current (DC) offset and generate not only a desired frequency signal but also a second order harmonic signal.
In particular, when signals having two frequencies f1 and f2 are input to a general non-linear circuit, signals having 2*f1, 2*f2, f1+f2, 3f1, 3f2, 2*f1−f2, 2f2−f1, 2f1+f2 or 2f2+f1, . . . frequencies are generated from, for example, the mixers 14 and 16 due to the non-linear properties of the mixers 14 and 16.
Normally, the undesired frequencies resulting from the non-linear properties of the mixers 14 and 16 are removed by means of, for example, the low pass filters 22 and 24. However, when the input frequencies f1 and f2 are almost equal and the desired frequency signal is the baseband signal, the frequencies of f1 and f2 may be in the range of the baseband frequencies and may not be removed by the filters 22 and 24. These unfiltered signals may then cause interferences between channels having small frequency differences from adjacent channels and signal distortions due to the interferences between the unfiltered signals themselves.
The f1 and f2 frequency signal is referred to as the IMD2. The degree of the linearity of a circuit is represented by the relationship between the ratio of the IMD2 and the amplification of the signal input to the circuit. The degree of the linearity is referred to as 2nd order intercept point (IP2). In addition, since the DCR shifts the desired signal to the baseband frequencies, the IMD2 generated from the mixers 14 and 16 may greatly deteriorate the performance of the DCR. Accordingly, the mixers 14 and 16 or a frequency mixer should have a high IP2 to reduce the ratio of the IMD2.
FIG. 2 is a circuit diagram showing a conventional Gilbert cell mixer. Referring to FIG. 2, the Gilbert cell mixer includes an emitter coupled pair of transistors Q1 and Q2 to which RF signals (RF+, RF−) are input, regeneration resistors RE1 and RE2, Gilbert cell core transistors Q3, Q4, Q5 and Q6, pull-up resistors R1 and R2, and differential output nodes NO1 and NO2.
In the Gilbert cell mixer, when second order harmonic signals (each of which is the same) are generated at each of the differential output nodes NO1 and NO2, the second order harmonic signals may be cancelled by each other and rejected by a common mode rejection property. However, when the second order harmonic signals have a phase and amplitude different from each other, the second order harmonic signals may not be cancelled due to a mismatch in their phases and amplitudes.
The mismatch may occur at the transistors Q1 and Q2, the resistors RE1 and RE2 and result from the duty ratio of the local oscillating signals and the RF signal. The mismatch at certain elements (resistors, transistors, etc.), is caused by the size difference between the elements and a difference in the concentration of impurities.
A feedback circuit for compensating for the non-linearity of the Gilbert cell mixer is disclosed in U.S. Patent Application Publication No. 2002-193089A1, and a system for reducing intermodulation distortion in a DCR is disclosed in PCT Laid Open Patent Publication No. WO 02/80384 A1. According to the disclosure in the U.S. Patent Application Publication No. 2002-193089A1, a bias voltage of the transistor in the Gilbert cell core is regulated in response to the voltage difference between the differential output nodes, so that the mismatch of the area of the transistor is compensated. In the PCT Laid Open Patent Publication No. WO 02/80384 A1, a frequency mixer detects an intermodulation signal included in an RF signal input to the frequency mixer, and applies a compensation signal to an output signal of the frequency mixer, so that intermodulation distortion in the output signal may be reduced.
Thus, there is a need for a circuit that reduces IMD2 and DC offset in DCRs.